In recent years, the electronic industry develops and prospers under the guidance of Moore's Law. However, with the needs such as enhancing the computing speed of electronic products, the techniques run into bottlenecks. Three-dimensional integrated circuit integration (3D IC integration) techniques has become one of answers to the current issue that the performance of the electronic products has to meet the needs.
Compared with conventional package techniques, 3D IC integration techniques have many advantages. For example, sizes of devices are smaller, signal loss is reduced, and electrical properties perform better, all of which are due to the utilization of a through silicon via (TSV).
The TSV has become one of the important cores in 3D IC integration techniques, and the fabrication costs of the TSV have to be considered carefully. In a three-dimensional integrated circuit system in package (3D IC SiP) structure having a typical TSV interposer, the TSV interposer carries chips above and below by utilizing microbump structures, and connects to a substrate or a printed circuit board (PCB) via a solder bump structure.
Usually, five steps are required to fabricate a TSV structure:
First step, laser drilling process or deep reactive ion etch (DRIE) process are utilized to form a via.
Second step, a plasma enhanced chemical vapor deposition (PECVD) method is utilized to deposit a dielectric deposition.
Third step, a physical vapor deposition (PVD) method is utilized to deposit a barrier/electroplating seed layer.
Fourth step, copper electroplating is utilized to fill the via (via Cu-filling).
Fifth step, a chemical and mechanical polishing (CMP) process is utilized to remove protruding or extra material.
Fabrication costs for the aforementioned five steps are listed from high to low as: PVD>PECVD>CMP>Electroplating>Etching.
More specifically, the 3D IC integration technique is one of the most effective structures for enhancing performance of electrical products, allows a plurality of chips to interconnect with one another and integrates more computing capability, memory, and other functions in a very small apparatus. However, the conventional 3D IC integration utilizing a TSV requires the use of processes such as PVD and PECVD. As a result, a technical limitation exists as an aspect ratio is hardly improved (a via cannot be completely filled with copper). Moreover, fabrication costs of a TSV is very high due to issues like costly vacuuming, dry process equipment and consumption materials.
Accordingly, it is urgent and requires solutions for solving an issue of high costs in making through silicon via (TSV) in terms of solving a technical problem of 3D IC integration.